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Military & Space Products
32K x 8 ROM--SOI
FEATURES
RADIATION * Fabricated with RICMOSTM IV Silicon on Insulator (SOI) 0.75 m Process (Leff = 0.6 m) * Total Dose Hardness through 1x106 rad(SiO2) * Typical Operating Power <15 mW/MHz * Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s * Dose Rate Survivability through 1x1011 rad(Si)/s * Neutron Hardness through 1x1014 cm-2 * SEU Immune * Latchup Free * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V 10% Power Supply OTHER * Read Cycle Times < 17 ns (Typical) 25 ns (-55 to 125C)
HX6656
* Packaging Options - 28-Lead Flat Pack (0.500 in. x 0.720 in.) - 28-Lead DIP, MIL-STD-1835, CDIP2-T28 - 36-Lead Flat Pack (0.630 in. x 0.650 in.)
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened ROM is a high performance 32,768 word x 8-bit read only memory with industrystandard functionality. It is fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environments. The ROM operates over the full military temperature range and requires only a single 5 V 10% power supply. The ROM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 15 mW/MHz in operation, and less than 5 mW when de-selected. The ROM operation is fully asynchronous, with an associated typical access time of 14 ns. Honeywell's enhanced SOI RICMOSTM IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOSTM IV process is a 5-volt, SIMOX CMOS technology with a 150 A gate oxide and a minimum drawn feature size of 0.75 m (0.6 m effective gate length--Leff). Additional features include tungsten via plugs, Honeywell's proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability.
HX6656
FUNCTIONAL DIAGRAM
A:0-8,12-13
11
Row Decoder
* * *
32,768 x 8 Memory Array
* * *
CE NCS
Column Decoder Data O utp ut
Q :0-7 8
NO E
CS * CE * OE (0 = high Z)
Signal
1 = enab led # Signal
A:9-11,14
4
All controls must b e enab led for a signal to p ass. (#: numb er of b uffers, default = 1)
SIGNAL DEFINITIONS
A: 0-14 Q: 0-7 NCS Address input pins which select a particular eight-bit word within the memory array. Data Output Pins. Negative chip select, when at a low level allows normal read operation. When at a high level NCS forces the ROM to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers except CE. If this signal is not used it must be connected to VSS. Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS and CE. If this signal is not used it must be connected to VSS. Chip enable, when at a high level allows normal operation. When at a low level CE forces the ROM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS input buffer. If this signal is not used it must be connected to VDD.
NOE
CE*
TRUTH TABLE
NCS L H X CE* H X L NOE L XX XX MODE Read Deselected Disabled Q Data Out High Z High Z
Notes: X: VI=VIH or VIL XX: VSSVIVDD NOE=H: High Z output state maintained for NCS=X, CE=X
*Not Available in 28-lead DIP or 28-Lead Flat Pack
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HX6656
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose The ROM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and ROM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The ROM will meet any functional or electrical specification after exposure to a radiation pulse of 50 ns duration up to 1x1011 rad(Si)/s, when applied under recommended operating conditions.
Neutron Radiation The ROM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.
Single Event Phenomena Transient Pulse Ionizing Radiation The ROM is capable of reading and retaining stored data during and after exposure to a transient ionizing radiation pulse of 1 s duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed on or near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through requirements, typical circuit board mounted de-coupling capacitors are recommended. All storage elements within the ROM are immune to single event upsets. No access time or other performance degradation will occur for LET 190 MeV/cm/mg2.
Latchup The ROM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter Total Dose Transient Dose Rate Upset (3) Transient Dose Rate Survivability (3) Neutron Fluence Limits (2) 1x106 1x109 1x1011 1x1014 Units rad(SiO2) rad(Si)/s rad(Si)/s N/cm2 Test Conditions
TA=25C Pulse width 1 s Pulse width 50 ns, X-ray, VDD=6.0 V, TA=25C 1 MeV equivalent energy, Unbiased, TA=25C
(1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55C to 125C. (3) Not guaranteed with 28-Lead DIP.
3
HX6656
ABSOLUTE MAXIMUM RATINGS (1)
Rating Symbol VDD VPIN TSTORE TSOLDER PD IOUT VPROT Parameter Positive Supply Voltage (2) Voltage on Any Pin (2) Storage Temperature (Zero Bias) Soldering Temperature * Time Total Package Power Dissipation (3) DC or Average Output Current ESD Input Protection Voltage (4) 28 FP/36 FP Thermal Resistance (Jct-to-Case) Junction Temperature 28 DIP 2000 2 10 175 Min -0.5 -0.5 -65 Max 7.0 VDD+0.5 150 270*5 2.5 25 Units V V C C*s W mA V C/W C
JC
TJ
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) ROM power dissipation (IDDSB + IDDOP) plus ROM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description Symbol VDD TA VPIN Parameter Supply Voltage (referenced to VSS) Ambient Temperature Voltage on Any Pin (referenced to VSS) Min 4.5 -55 -0.3 Typ 5.0 25 Max 5.5 125 VDD+0.3 Units V C V
CAPACITANCE (1)
Symbol CI CO Parameter Input Capacitance Output Capacitance Typical (1) Worst Case Min Max 7 9 Units pF pF Test Conditions
VI=VDD or VSS, f=1 MHz VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
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HX6656
DC ELECTRICAL CHARACTERISTICS
Symbol IDDSB1 Parameter Static Supply Current Typical Worst Case (2) Units (1) Min Max 1.5 1.5 4.0 -1 -1 CMOS TTL CMOS TTL
0.7xVDD
Test Conditions
VIH=VDD IO=0 VIL=VSS Inputs Stable NCS=VDD, IO=0, f=40 MHz f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS VSSVIVDD VSSVIOVDD Output=high Z
mA mA mA A A V V V V
IDDSBMF Standby Supply Current - Deselected IDDOPR II IOZ VIL Dynamic Supply Current, Selected Input Leakage Current Output Leakage Current Low-Level Input Voltage
+1 +1
0.3xVDD
0.8
VDD = 4.5V
VIH
High-Level Input Voltage
2.2 0.4 0.05 4.2
VDD-0.05
VDD = 5.5V VDD = 4.5V, IOL = 10 mA VDD = 4.5V, IOL = 200 A VDD = 4.5V, IOH = -5 mA VDD = 4.5V, IOH = -200 A
VOL
Low-Level Output Voltage
V V V V
VOH
High-Level Output Voltage
(1) Typical operating conditions: VDD= 5.0 V,TA=25C, pre-radiation. (2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55C to +125C, post total dose at 25C. (3) All inputs switching. DC average current.
2.9 V Vref1 249 DUT output Vref2
+ -
Valid high output
+ -
Valid low output
CL >50 pF* *CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
HX6656
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3) Symbol Parameter Typical (2) TAVAVR TAVQV TAXQX TSLQV TSLQX TSHQZ TEHQV TEHQX TELQZ TGLQV TGLQX TGHQZ Address Read Cycle Time Address Access Time Address Change to Output Invalid Time Chip Select Access Time Chip Select Output Enable Time Chip Select Output Disable Time Chip Enable Access Time (4) Chip Enable Output Enable Time (4) Chip Enable Output Disable Time (4) Output Enable Access Time Output Enable Output Enable Time Output Enable Output Disable Time 0 9 5 10 9 5 10 25 3 25 -55 to 125C Min 25 25 Max ns ns ns ns ns ns ns ns ns ns ns ns Units
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=5.0 V, TA=25C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55C to +125C, post total dose at 25C. (4) Chip Enable (CE) pin not available on 28-lead FP or DIP.
TAVAVR
ADDRESS
TAVQV TSLQV TAXQX
NCS
TSLQX TSHQZ DATA VALID
DATA OUT
HIGH IMPEDANCE TEHQX TEHQV
TELQZ
CE
TGLQX TGLQV TGHQZ
NOE
6
HX6656
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle The ROM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high, and toggling the addresses. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the ROM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the I/O until TAXQX time following the next sequential address transition. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS, however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition.
7
HX6656
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
3V
CMOS I/O Configuration
VDD-0.5 V
Input Levels*
1.5 V 0V 0.5 V
VDD/2
1.5 V
VDD/2
Output Sense Levels
High Z
VDD-0.4V 0.4 V 3.4 V 2.4 V
High Z
VDD-0.4V 0.4 V 3.4 V High Z 2.4 V
High Z
High Z = 2.9V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a complete "Total Quality Assurance System," a computer data base process performance tracking system, and a radiation-hardness assurance strategy. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as product die, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883C TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. need to create detailed specifications and offer benefits of improved quality and cost savings through standardization.
RELIABILITY
Honeywell understands the stringent reliability requirements for space and defense systems and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOSTM process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. In addition, the reliability of the RICMOSTM process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer's requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product.
SCREENING LEVELS
Honeywell offers several levels of device screening to meet your system needs. "Engineering Devices" are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MILSTD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Military Drawing (SMD). QML devices offer ease of procurement by eliminating the 8
HX6656
PACKAGING
The 32K x 8 ROM is offered in a custom 36-lead flat pack (FP), 28-Lead FP, or standard 28-lead DIP. Each package is constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. The 36-lead FP also features a non-conductive ceramic tie bar on the lead frame. The tie bar allows electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. Ceramic chip capacitors can be mounted to the package to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package. All NC (no connect) pins should be connected to VSS to prevent charge build up in the radiation environment.
28-LEAD FP PINOUT
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
36-LEAD FP PINOUT
VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VSS VDD NWE CE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS
Top View
VDD NWE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3
Top View
36-LEAD FLAT PACK
E
1
22018131-001
Top View
b (width)
D G
e (pitch)
H
L
L
Ceramic Body
J A
Kovar Lid [3]
NonConductive Tie-Bar
0.004 N M
I
C
X VDD VSS
Optional Capacitors
VDD
VSS
S A b C D E e F G H I J L
All dimensions are in inches [1]
0.095 0.014 0.008 0.002 0.005 to 0.0075 0.650 0.010 0.630 0.007 0.025 0.002 [2] 0.425 0.005 [2] 0.525 0.005 0.135 0.005 0.030 0.005 0.080 typ. 0.285 0.015 M N O P R S T U V W X Y 0.008 0.003 0.050 0.010 0.090 ref 0.015 ref 0.075 ref 0.113 0.010 0.050 ref 0.030 ref 0.080 ref 0.005 ref 0.450 ref 0.400 ref
F
Y
1
1
O V
W P R T U
[1] Parts delivered with leads unformed [2] At tie bar [3] Lid tied to VSS
9
HX6656
28-LEAD FLAT PACK (22017842-001)
E 1 b
(width) Index
All dimensions in inches 1
A b C D e E E2 E3 F G L Q S U W X Y 0.105 0.015 0.017 0.002 0.003 to 0.006 0.720 0.008 0.050 0.005 [1] 0.500 0.007 0.380 0.008 0.060 ref 0.650 0.005 [2] 0.035 0.004 0.295 min [3] 0.026 to 0.045 0.045 0.010 0.130 ref 0.050 ref 0.075 ref 0.010 ref
e
(pitch)
D
F
TOP VIEW
BOTTOM VIEW
S
U L W X Y
Kovar Lid [4] Ceramic Body Capacitor Pads
Q
G
A
C
Lead Alloy 42 [3]
[1] [2] [3] [4]
BSC - Basic lead spacing between centers Where lead is brazed to package Parts delivered with leads unformed Lid connected to VSS
E2
E3
28-LEAD DIP (22017785-001)
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
10
HX6656
DYNAMIC BURN-IN DIAGRAM*
VDD
F16 F7 F6 F5 F4 F3 F2 F8 F13 F14 F1 F1 F1
R R R R R R R R R R R R R
STATIC BURN-IN DIAGRAM*
VDD
R
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
R R R R R R R R R R R R
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VSS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
VDD NC A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R R R R R R R R R R R R R
F0 F15 F12 F11 F10 F17 F9 F17 F1 F1 F1 F1 F1
VSS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
VDD NC A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R R R R R R R R R R R R R R
32K x 8 ROM
VDD = 6.5V, R 10 K, VIH = VDD, VIL = VSS Ambient Temperature 125 C, F0 100 KHz Sq Wave Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
VDD = 5.5V, R 10 K Ambient Temperature 125 C
*36-lead Flat Pack burn-in diagrams have similar connections and are available on request.
ROM CODE
The ROM code can be provided to Honeywell via FTP, E-Mail or a variety of magnetic storage media, including 3.5 inch floppy disc, 4m digital tape and others. The ROM Code data file should contain the following format:

[/] [;] [Comment] Where items enclosed in `[`and']' are optional. The address and data must be hex numbers in the form, MSB...LSB. The "/" and the ";" are optional and any characters after the "#" are comments. For example the following input file, all of the lines are valid: 000 d4 001 / 32 002 1d 003 / 72; 4/5e; # all of these lines are in valid format
11
32K x 8 ROM
HX6656
ORDERING INFORMATION (1) H X 6656
PART NUMBER
N
S
H
C
PROCESS X=SOI SOURCE H=HONEYWELL
SCREEN LEVEL INPUT V=QML Class V BUFFER TYPE Q=QML Class Q C=CMOS Level S=Level S T=TTL Level TOTAL DOSE PACKAGE DESIGNATION B=Level B HARDNESS N=28-Lead FP E=Engr Device (2) R=1x105 rad(SiO2) R=28-Lead DIP F=3x105 rad(SiO2) X=36-Lead FP H=1x106 rad(SiO2) K=Known Good Die N=No Level Guaranteed - = Bare die (No Package)
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information. (2) Engineering Device description: Parameters are tested from -55 to 125C, 24 hr burn-in, no radiation guaranteed. Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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